(1) Field of the Invention
The present invention relates to a highly integrated semiconductor integrated circuit device (IC), and more particularly to photoresist check patterns in an IC of a kind which is provided with multi-level interconnect layers.
(2) Description of the Related Art
In recent years, along with the progress in high integration of semiconductor elements formed within a semiconductor substrate, there have been advancements in miniaturization and integration of circuit interconnect patterns which are formed on a surface of the substrate with insulating films interposed therebetween, and the advancements have reached a state wherein the patterns are required to be smaller than 0.5 .mu.m in their line widths.
In realizing the miniaturization and high integration of elements within a semiconductor substrate, it is required to maintain, in miniaturizing and highly integrating the circuit interconnect patterns also on a surface of the substrate, the same degree of resolution as in the real image of the shield mask formed on the photoresist film during the lithography process.
Further, along with the advancement in the miniaturization, the elements concerned are becoming more complex in a three dimensional aspect. Particularly, in the dynamic RAM (DRAM) of MOS type, in order to attain the necessary charge capacitance in a very small area, it is required that the charge electrode structure be higher in its height in a vertical direction and be more complex in its shape as, for example, a stack type capacitor cell structure in which memory cells are disposed on a silicon substrate.
However, since there is a limit in the depth of focus (DOF) in the reduction step-and-repeat projection device (stepper) normally used in the exposure of the photoresist, it is becoming more difficult to attain a sufficient DOF for the miniaturized patterns described above.
Therefore, in a process for fabricating highly integrated ICs, the detection of regions with defective resolution, such as cuts at steps or short-circuiting (connection) of photoresist patterns, is extremely important.
Conventionally, for detecting defective regions in the photoresist patterns, there has been used a photoresist check pattern as shown in FIGS. 1 and 2. Shown in FIGS. 1 and 2 is an example of the check pattern in a highly integrated IC.
FIG. 1 is a top view of the photoresist check pattern, and FIG. 2 is a sectional view taken along line 2X-2X' in FIG. 1.
A process for fabricating a conventional check pattern is explained with reference to FIG. 2. First, by a known process, a field oxide film 2 is formed on a surface of a semiconductor substrate 1, and then a gate oxide film 3 is formed by thermal oxidation.
Next, after patterning the gate electrode 4 in polysilicon, an interlayer film 5 (the interlayer film here is an insulating film of such as silicon oxide and boron phosphosilicate glass (BPSG)), and a first polysilicon interconnect layer 6 is patterned, followed by formation of an interlayer film 7.
Then, a first aluminum interconnect layer 8 is deposited, and photoresists 9a, 9b and 9c are patterned. Subsequently, by using the photoresists 9a, 9b and 9c as masks, aluminum etching is carried out and the first aluminum interconnect layer is patterned.
FIGS. 1 and 2 represent a state of the process prior to the patterning of the first aluminum interconnect layer by etching.
In this conventional process, the photoresist patterns 9a, 9b and 9c are formed as check patterns respectively on three different levels of surfaces, and the presence of any regions of defective resolution are checked by confirming the resolution of the photoresists on all these levels of surfaces. When the photoresist patterns 9a, 9b and 9c on all these level surfaces are resolved into appropriate shapes, the resolution is judged as acceptable. The surfaces of the photoresist patterns 9a, 9b and 9c are made substantially flat so that good resolution can be obtained.
However, the patterns actually used in the ICs have complex shapes, and there are possibilities in which, for example, the pattern as shown in FIG. 3 exists.
The photoresist pattern shown in FIG. 3 exhibits sensitivity curves as shown in FIG. 4. Where, for example, the thickness is T.sub.1, the minimum resolution exposure time will be E.sub.1, and where the same is T.sub.2, such time will be E.sub.2. Thus, the minimum resolution exposure time is longer in the case where the thickness is thinner T.sub.2.
Therefore, in the example shown in FIG. 3, where the photoresist is applied with the thickness thereof being determined at the surface for T.sub.1, the thickness T.sub.2 exists locally, leading to a high likelihood wherein, after the exposure and development, only the photoresist region whose thickness is T.sub.2 remains.
When the problem as above has occurred, the photoresists 9d and 9e are connected, as shown in FIG. 5, so that the etching of the aluminum interconnect layer in such a state results in an interconnection failure. FIG. 3 represents a sectional view taken along line 3X-3X' of FIG. 5.
With the conventional check pattern arrangement shown in FIGS. 1 and 2, it was not possible to check the interconnection failure as described above. That is, in the conventional check pattern arrangement, the check patterns 9a, 9b and 9c were of the same height at the resist surfaces with the thicknesses of the check patterns being different from one another, so that the respective patterns 9a, 9b and 9c behaved differently in terms of the sensitivity curves as shown in and explained for FIG. 4. Despite such differences, the focus and the exposure time were so set that the check patterns at the three step regions should result all in an adequate patterning. In this way, it was not possible for the check patterns to detect the state of cuts at the sloped regions between the steps.
Furthermore, in a circuit pattern whose surface contains a concave region as shown in FIG. 6, an optical halation develops during the exposure from within the gate electrode having the concave region thereby causing the photoresist pattern 9f to be locally constricted and, in the worse case, causing lines to be broken. FIG. 7 represents a sectional view taken along line 7X-7X' in FIG. 6.
With the conventional check patterns, it has not been possible to check the problems as explained above.
A conventional method for detecting a defective pattern at a step region in a circuit pattern constituted by fine patterns on a wafer has been disclosed, for example, in Japanese Patent Application Kokai Publication No. Sho 62-78818. In the disclosed method, as in the prior art method described above, the pattern test region is provided on the wafer, and the steps formed in this region during each of the formation processes include at least a step region in which a resist pattern defect is likely to occur, and a check pattern is formed across these steps.
However, with the conventional circuit pattern detection method disclosed in the above identified Japanese Patent Application Kokai Publication No. Sho 62-78818, it is not possible to detect a defect in a photoresist pattern caused by the halation occurred in the light from inside the interconnect layer having a concave region. Further, in the method disclosed in the above publication, since the thicknesses of the photoresist layer is assumed to be substantially constant, the disclosed conventional detection method does not serve as a solution to a problem requiring the detection of such a defect in a resist pattern that occurs by differences in the sensitivity characteristics due to differences in the thicknesses of photoresist at the step regions.